1. Field of the Invention
The present invention relates to semiconductor devices, and more particularly to a semiconductor device having a memory unit that is capable of reducing power consumption.
2. Description of the Background Art
In recent years, static random access memories (hereinafter also referred to as SRAMs), multi-port memories, and the like that are incorporated in system LSIs or the like tend to have a larger storage scale and a higher operating frequency. With this tendency, the increase in operating power has been a problem in the SRAMs and the like. With the SRAMs and the like, the charge/discharge current caused by the oscillation of a signal in bitlines takes up a large proportion in the operating power. Thus, in order to reduce the operating power in SRAMs and the like, it is important to reduce the charge/discharge current in the bitlines.
In the case of SRAM, as the potential of a wordline rises in reading data, the potential of one of bitline pair gradually reduces according to the data retained in a memory cell circuit. Concurrently, the potential of one of the IO line pair selected by a column decoder, among the IO line pairs connected to the bitline pair, reduces likewise. At the time when a sufficient potential difference in the bitline pair (IO line pair) can be obtained, the potential difference in the IO line pair is amplified by a sense amplifier circuit to determine whether the data contained within the target cell is “1” or “0”.
Ideally, if the wordline is deactivated at the time the sense amplifier circuit determines the data, the potential of one of the bitline pair does not continue to reduce after the foregoing time, and it is thus possible to prevent wasteful current from flowing and unnecessary power from being consumed. However, in order to deactivate the wordline with that timing, optimization in timing design is difficult; thus, it has been necessary to provide an operation margin when taking process variations and the like into consideration. In other words, to ensure an operation margin, it has been necessary to provide a certain period of time from the foregoing time until the wordline is deactivated.
If a large operation margin before the wordline is deactivated is provided as described above, the potential of the bitline pair reduces unnecessarily during that period because of the activated memory cell. This causes a problem that a wasteful current flows through the bitline pair and a more power than is necessary is required in precharging.
To solve the foregoing problem, a method of locally deactivating a wordline using a replica circuit is proposed in “A Replica Technique for Wordline and Sense Control in Low-Power SRAM's,” IEEE Journal of Solid-State Circuits, Vol. 33, pp. 1208-1219, August 1998.
The method proposed in the foregoing reference, however, merely intends to locally control the time for deactivating a wordline using the replica bitline, and it does not necessarily guarantee that the time for determining data is always earlier than the time for deactivating the wordline. Therefore, the time for determining data can be later than the time for deactivating the wordline depending on the semiconductor devices because of process variations.
If the time for determining data becomes later, a sufficient potential difference in a bitline pair cannot be obtained and consequently correct data may not be read out by the sense amplifier circuit. For this reason, it has been necessary even in the case of the method proposed in foregoing reference to ensure an operation margin so that data is retrieved by the sense amplifier circuit and after a short while the wordline is deactivated. That is, even with the method proposed in the foregoing reference, the potential of the bitline pair continues to reduce during the time from the time data is determined until the wordline is deactivated because an operation margin needs to be ensured, and consequently unnecessary power is wasted.